1. Field of the Invention
The present invention relates to a high frequency switching circuit device which is made of metal-semiconductor field effect transistor stages formed on a compound semiconductor substrate, and which is appropriate for use in a communication terminal device, such as a cellular phone.
2. Prior Art
Accessing styles and radio transmission frequencies differ, depending on the standard in communication systems for cellular phones. Therefore, it is necessary to carry around cellular phones that conform to the respective standards of the country or region where the service is utilized, or to carry around one multi-band cellular phone which can be used with a number of communication systems, in order to be able to utilize a cellular phone in a number of regions in the world.
In the latter case, a cellular phone may be formed of parts that have been manufactured for the respective communication systems, so that one cellular phone can be utilized with a number of communication systems. However, the volume and the weight increase in proportion to the number of systems with which the phone can be used. Such a phone is not suitable as a portable device. Therefore, it has become necessary to provide compact lightweight high frequency parts that can be used with a number of systems.
Radio waves in a GHz band are utilized at the time of communication in mobile communication terminals such as cellular phones. At this point, field effect transistor stages made of gallium arsenic (GaAs) having excellent frequency properties at high frequencies are utilized as switching elements in antenna switching circuits, transmission/reception switching circuits and the like.
In such a field effect transistor stage, a voltage at the H level (for example, 3 V) is applied to the gate voltage terminal as a gate bias voltage that is sufficiently higher than the pinch off voltage, so as to provide a low impedance between the drain and the source, and thereby, the field effect transistor stage can be converted to the ON state. Conversely, a voltage at the L level (for example, 0 V) is applied to the gate voltage terminal as a gate bias voltage that is sufficiently lower than the pinch off voltage, so as to provide a high impedance between the drain and the source, and thereby, the field effect transistor stage can be converted to the OFF state.
FIG. 13 is a circuit diagram showing an example of a high frequency switching circuit device having the first configuration according to the prior art, where a switching element as that described above is used. This high frequency switching circuit device can be utilized, for example, as an antenna switching part. Here, an SP3T (single-pole triple-throw) switch for high frequency, which is one type of a high frequency switching circuit device, is shown as an example.
The SP3T switch for high frequency switches the output path of, for example, an inputted high frequency signal, and a first high frequency signal terminal RF1 is placed on its input side. In addition, a second high frequency signal terminal RF2, a third high frequency signal terminal RF3 and a fourth high frequency signal terminal RF4 are placed on the output side. High frequency signals that have been inputted into first high frequency signal terminal RF1 are outputted from any of second high frequency signal terminal RF2, third high frequency signal terminal RF3 and fourth high frequency signal terminal RF4. The input/output relationship of the switch may be inverted from that described above.
A first field effect transistor stage FET1, which is a switching circuit for switching a high frequency signal path, is provided between first high frequency signal terminal RF1 and second high frequency signal terminal RF2. In addition, a second field effect transistor stage FET2, which is the same type of switching circuit, is provided between first high frequency signal terminal RF1 and third high frequency signal terminal RF3. A third field effect transistor stage FET3, which is the same type of switching circuit, is provided between first high frequency signal terminal RF1 and fourth high frequency signal terminal RF4. In the following, field effect transistor stage means a switching circuit where a field effect transistor stage is used as a switching element.
Thus, a control voltage that is supplied to a first control voltage input terminal CTL1, a second control voltage input terminal CTL2 and a third control voltage input terminal CTL3 allows respective field effect transistor stages FET1, FET2 and FET3 to undergo ON/OFF control. As a result of this, first high frequency signal terminal RF1 is electrically connected to any one of second high frequency signal terminal RF2, third high frequency signal terminal RF3 and fourth high frequency signal terminal RF4. Here, symbols R1, R2 and R3 indicate resistors which are connected to the gates of the field effect transistors of first field effect transistor stage FET1, second field effect transistor stage FET2 and third field effect transistor stage FET3, respectively.
On the other hand, in the case where such GaAs FET's are used for a switching element, a problem rises where it is difficult to provide both low insertion loss and high isolation. The width of the gate voltage terminal of a single FET may be reduced so that high isolation can be gained in the FET. In the case where the width of the gate voltage terminal is reduced, however, a problem arises where ON resistance increases, and therefore, insertion loss increases. Accordingly, it is difficult to provide both low insertion loss and high isolation. Though as described above, it is difficult to provide low insertion loss and high isolation in a single FET, this problem has been solved by combining FET's.
FIG. 14 is a circuit diagram showing an example of a high frequency switching circuit device having the second configuration according to the prior art. Here, an SP3T switch for high frequency is shown as an example where one series FET and one shunt FET are combined with each signal path.
In this configuration, the RF signal that leaks via a capacitance component of the series FET in the OFF state can be led to the ground by the shunt FET in the ON state, and thereby, high isolation can be gained.
In this high frequency switching circuit device, a fourth field effect transistor stage FET 4 is placed between second high frequency signal terminal RF2 and the grounding terminal GND. As a result of this, the signal that leaks from first high frequency signal terminal R1 to second high frequency signal terminal R2 via first field effect field transistor stage FET1 is led to the ground when first high frequency signal terminal RF1 and second high frequency signal terminal RF2 are in the state of being cut off. In the same manner, a fifth field effect transistor stage FET5 is placed between third high frequency signal terminal RF3 and grounding terminal GND. Furthermore, a sixth field effect transistor stage FET6 is placed between fourth high frequency signal terminal RF4 and grounding terminal GND.
As described above, in this switching circuit, a shunt circuit is formed of fourth field effect transistor stage FET4, fifth field effect transistor stage FET5 and sixth field effect transistor stage FET6. Symbols R4, R5 and R6 indicate resistors which are connected to the gates of the field effect transistors of fourth field effect transistor stage FET4, fifth field effect transistor stage FET5 and sixth field effect transistor stage FET6, respectively. Symbols C1, C2 and C3 indicate capacitors which are connected in series to fourth field effect transistor stage FET4, fifth field effect transistor stage FET5 and sixth field effect transistor stage FET6.
These field effect transistor stages FET1 to FET6 undergo ON/OFF control by means of a control voltage that is supplied to first control voltage input terminal CTL1 to sixth control voltage input terminal CTL6.
Concretely speaking, as shown in the control logic table of FIG. 15, fifth control voltage input terminal CTL5 and sixth control voltage input terminal CTL6 become of the high state when first control voltage input terminal CTL1 becomes of the high state. In the same manner, fourth control voltage input terminal CTL4 and sixth control voltage input terminal CTL6 become of the high state when second control voltage input terminal CTL2 becomes of the high state. In addition, fourth control voltage input terminal CTL4 and fifth control voltage input terminal CTL5 become of the high state when third control voltage input terminal CTL3 becomes of the high state. As a result, isolation properties between the respective high frequency signals are appropriately maintained.
In order to adopt the configuration of an SP3T switching circuit for high frequency that has such a shunt FET for securing isolation, however, control voltage input terminals for three systems become necessary only to control the control voltages that are independently applied to the gate voltage terminals of the respective shunt FET's. Accordingly, control voltage input terminals for six systems, including those for controlling the series FET's, become necessary. As a result, a problem arises where the number of pins for the package of the high frequency switching circuit device increases and the size of the package increases, and thus, the configuration is unsuitable for a portable terminal where miniaturization of the device is required.
The first method, which is the simplest method, for avoiding an increase in the number of the control voltage input terminals as described above is to adopt a configuration of a high frequency switching circuit device having the third configuration according to the prior art, as shown in FIG. 16. That is to say, one series FET and two shunt FET's are combined with each signal path.
Concretely speaking, in the SP3T switch configuration shown in the above, a seventh field effect transistor stage FET7 is added between second high frequency signal terminal RF2 and grounding terminal GND. In addition, in the same manner, an eighth field effect transistor stage FET8 is added between third high frequency signal terminal RF3 and grounding terminal GND. Furthermore, a ninth field effect transistor stage FET9 is added between fourth high frequency signal terminal RF4 and grounding terminal GND.
Thus, first control voltage input terminal CTL1 allows first field effect transistor stage FET1, fifth field effect transistor stage FET5 and sixth field effect transistor stage FET6 to undergo ON/OFF control. In the same manner, second control voltage input terminal CTL2 allows second field effect transistor stage FET2, fourth field effect transistor stage FET4 and ninth field effect transistor stage FET9 to undergo ON/OFF control. Furthermore, third control voltage input terminal CTL3 allows third field effect transistor stage FET3, seventh field effect transistor stage FET7 and eighth field effect transistor stage FET8 to undergo ON/OFF control.
As a result, control voltage input terminals for three systems allow isolation to be appropriately maintained. Symbols R7, R8 and R9 indicate resistors which are connected to the gates of seventh field effect transistor stage FET7, eighth field effect transistor stage FET8 and ninth field effect transistor stage FET9, respectively. Symbols C4, C5 and C6 indicate capacitors which are connected in series to seventh field effect transistor stage FET7, eighth field effect transistor stage FET8 and ninth field effect transistor stage FET9, respectively.
In addition to the above, a second method for eliminating the control voltage input terminal for the SPDT switch by incorporating a differential amplifier circuit and a symmetrical control voltage generation circuit by means of an inverter circuit into a high frequency switching circuit device is disclosed in Patent Document 1. In addition, a third method for eliminating the control voltage input terminal by connecting the control voltage input terminal of the series FET to the grounding terminal, connecting the drain or the source of the shunt FET to the power supply terminal, and applying the control voltage of the shunt FET to the drain or the source of the Series FET is disclosed in Patent Document 2.
Patent Document 1: Japanese Unexamined Patent Publication H6 (1994)-85641
Patent Document 2: Japanese Unexamined Patent Publication H11 (1999)-150464
According to the above described methods, however, the following problems arise.
According to the above described first method, the number of FET's increases, increasing the size of the GaAs chip. In addition, together with this, one shunt FET is added to each signal path, and thereby, an FET in the OFF state, that is to say, a capacitance component, is added to the ON path in such a manner as to be connected in parallel. Therefore, frequency properties of the insertion loss of the ON path deteriorate.
In addition, according to the second method, it is extremely difficult to fabricate a differential amplifier circuit and an inverter circuit within a GaAs chip. Therefore, the number of external pins increases, the number of parts increases, and the number of total process steps for the formation of FET's increases.
Furthermore, according to the third method, the drain or source voltage of each FET is controlled, and therefore, it is necessary to connect a capacitor for cutting a DC anterior or posterior the drains and the sources of many FET's. Accordingly, it is necessary to incorporate a large number of capacitors in a high frequency switching circuit, and the area of the chip and the number of parts increases.